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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? single chip mixer/oscillator pll combination for multi band tuner for dtt applications ? each mixer oscillator band optimized for wide dynamic range ? rf input stages allow for either single-ended or differential drive ? pll frequency synthesizer designed for low phase noise performance ? broadband output level detect with onset adjust ? pll frequency synthesizer compatible with standard digital terrestrial offsets ? four integrated switching ports ?i 2 c fast mode compliant ? esd protection (normal esd handling procedures should be observed) applications ? terrestrial digital receiver systems ? terrestrial analogue receiver systems ? cable receiver systems ? data communications systems description the sl2610 is a mixer oscillator intended primarily for application in all band tuners, where it performs image reject downconversion of the rf channel to a standard 36 mhz or 44 mhz if. each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank. the band outputs share a common low impedance sawf driver stage. frequency selection is controlled by the on-board i 2 c bus frequency synthesizer. this block also controls four general purpose switching ports for selecting the prefilter/agc stages. october 2004 ordering information sl2610/ig/lh1q 40 pin mlp tape & reel, bake & drypack sl2610/ig/lh1n 40 pin mlp trays, bake & drypack sl2610/ig/lh2q 40 pin mlp tape & reel, bake & drypack* sl2610/ig/lh2n 40 pin mlp trays, bake & drypack* *leadfree -40 c to +85 c sl2610 wide dynamic range image reject mopll data sheet figure 1 - sl2610 block diagram hi convop ~~ ~ band lo band mid band convopb ifip ifipb ifop ifopb agc bias agc out hi band lo band mid band i 2 c interface port interface ref divider ~ port p0 port p1 port p2 port p3 prog divider charge pump drive xtal xtalcap sda scl add if select
sl2610 data sheet 2 zarlink semiconductor inc. the sl2610 has high intermodulation intercept performance so offering high signal to spurious performance in the presence of higher amplitude interferers or in t he presence of a wide bandwidth composite input signal. an output broadband level detect circuit is included for control of the tuner front end agc. figure 2 - pin allocation diagram quick reference data characteristics units frequency range: low band 50-500 mhz mid band 50-500 mhz high band 200-900 mhz conversion gain * 32 2db noise figure 13 db typical image reject 35 db p1db input referred, converter section only 106 dbuv ip3 input referred, converter section only 14 dbm ip2 input referred, converter section only 48 dbm lo phase noise (free running) @ 10 khz offset -90 dbc/hz @ 100 khz offset -110 dbc/hz pll phase noise -158 dbc/hz maximum composite output amplitude 3 dbm * assuming 2 db shaping filter loss in external if path. lh40 port p3 vccrf hi input port p2 port p1 mid input lolowop lolowopb lomidop vcclo lohiip lohiop lohiopb lohiipb vcclo mid inputb vccrf lo input ifopb ifop agcbias vccif ifipb ifip add convop convopb vccdig lo inputb vccrf agcout port p0 charge pump xtal cap drive xtal sda scl lomidopb hi inputb vee (package paddle) pin 1
sl2610 data sheet 3 zarlink semiconductor inc. figure 3 - sl2610 evaluation board schematic c14 2p2 c13 2p2 c12 2p2 c11 2p2 l5 22nh l6 8n2h c16 100pf c15 5pf r6 4k7 gnd sda 3 vdd 4 gnd 5 scl 6 cn1 i2c gnd r11 4k7 r10 4k7 +5v c17 100nf c19 47pf c18 47pf x1 4 mhz gnd c20 47pf r7 33k tr1 bcw31 gnd r8 20k +30v r9 18k c21 1n5f gnd vt +5v +5v +5v +5v +5v +5v l4 82nh d2 bb640 c10 7pf l3 36nh l2 1u5h c2 6p8f l1 120nh d1 bb640 r2 1k r4 4k7 vt r5 1k l7 220nh l8 220nh c27 82pf c26 82pf +5v c24 1nf c25 1nf t1 5:1 sk4 if out gnd c3 1nf c4 1nf c5 1nf c6 1nf c7 1nf c8 1nf sk1 hi in sk2 mid in sk3 low in gnd gnd gnd r3 1k gnd 1 2 3 cn2 gnd +30v gnd +5v c29 10nf c30 10nf c31 10nf c32 10nf c33 10nf c34 10nf c35 10nf gnd c36 470uf +30v c28 100nf gnd d4 p0 d5 p1 d6 p2 d7 p3 r12 750r r13 750r r14 750r r15 750r +5v p0 p1 p2 p3 p0 p1 p2 p3 +5v c22 10nf c23 10nf 1 2 3 cn3 address gnd c1 100pf r1 4k7 gnd gnd c9 100pf r16 20r r17 10r r18 10r d3 bb555 r19 10r r20 10k port p3 1 vcc rf 2 high ip 3 high ip b 4 port p2 5 port p1 6 mid input 7 mid ip b 8 vcc rf 9 lo input 10 lo input b 11 vcc rf 12 agc out 13 port p0 14 drive 15 charge pump 16 xtal cap 17 xtal 18 sda 19 scl 20 vcc dig 21 conv op b 22 conv op 23 add 24 if input 25 if input b 26 vcc if 27 agc bias 28 if o/p 29 if o/p b 30 vcclo 31 lohii/pb 32 lohio/pb 33 lohio/p 34 lohii/p 35 vcclo 36 lomidopb 37 lomidop 38 lolowopb 39 lolowop 40 vee = pin 0 = package paddle gnd 0 ic1 sl2610 vr1 10k +5v gnd gnd gnd gnd gnd gnd gnd gnd tp2 tp tp1 tp power if out agc address i2c control rf in (high) rf in (mid) rf in (low) gnd gnd gnd gnd
sl2610 data sheet 4 zarlink semiconductor inc. figure 4 - sl2610 evaluation board layout (top) figure 5 - sl2610 evaluation board layout (bottom)
sl2610 data sheet 5 zarlink semiconductor inc. 1.0 functional description the sl2610 is a multi band rf mixer oscillator with image reje ct and on-board fr equency synthesizer. it is intended primarily for application in all band te rrestrial tuners and requires a minimum external component count. it contains all elements required for rf downconversion to a standard if with the exception of external vco tank circuits. the pin allocation is contained in figure 2 and the block diagram in figure 1. 1.1 mixer/oscillator section in normal application the rf input is interfaced to the selected mixe r oscillator preamplifi er through the tuner prefilter and agc stages. the mixer input is arranged such that the signal can be coupl ed either differentially or single-ended, and achieves the specified minimum perfor mance in both configurations. band input impedances and nf are contained in figure 11 and figure 12 respecti vely. the converter two tone input spectra are contained in figure 13 and figure 14. the preamplifier output then feeds the mixer stage where the required ch annel is image reject downconverted to the if frequency. the local oscillator frequency for the downconversion is obtained from the on board local oscillator, which uses an external varactor tuned tank. typical vco applications are contained in figures 8, 9 and 10. the output of the mixer is then fed to the converter output driv er which presents a matched 200 ? differential load to an external if shaping filter. the output of the shaping filter is then coupled into the ifamp stage, whic h provides further gain and offers a 50 ? output impedance to interface direct with the tuner saw filter. the sl2610 contains a broadband level detect circuit whose output can be used to control the tuner agc. the target level of the agc detector is controlled by the volt age applied to the agcbias pin. the characteristic of the target level is given in figure 18. 1.2 pll frequency synthesizer the pll frequency synthesizer section contains all the el ements necessary, with the exception of a frequency reference and loop filter, to control a varicap tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generat ion of a loop with good phase noise performance. it can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (dtt) receivers. the lo signal is multiplexed from the selected oscillator section to an internal preamp lifier which provides gain and reverse isolation from the di vider signals. the output of the preamplifi er interfaces direct with the 15-bit fully programmable divider which is of mn+a architecture, w here the dual modulus prescaler is 16/17, the a counter is 4-bits and the m counter is 11 bits. the output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency. this fr equency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the referenc e frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in table 1. the output of the phase detector feeds a charge pump and loop amplifier section which when used with an external loop filter integrates t he current pulses into the varactor line voltage. the programmable divider out put fpd, divided by two and the reference di vider output fcomp, can be switched to port p0 by programming the device into test mode. the test modes are described in table 5.
sl2610 data sheet 6 zarlink semiconductor inc. 2.0 programming the sl2610 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats. data and clock are fed in on the sda and scl lines respectively as defined by i 2 c bus format. the synthesizer can either accept data (write mode) or send data (read mode) . the lsb of the address byte (r/w) sets the device into write mode if it is low and r ead mode if it is high. tables 2 and 3 illustra te the format of the data. the device can be programmed to respond to several addresses, which enabl es the use of more than one synthesizer in an i 2 c bus system (tables 2 and 3). table 4 shows how the address is selected by applying a voltage to the ?add? input. when the device receives a valid address byte, it pulls t he sda line low during the acknowledge period and during following acknowledge periods after further data bytes ar e received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line lo w during this period the device generates an internal stop condition whic h inhibits further reading. 2.1 write mode with reference to table 2, bytes 2 and 3 contain frequency information bits 2 14 -2 0 inclusive. byte 4 controls the reference divider ratio bits r4-r0 (table 1) and the charge pump setting bits c1-c0 (table 6). byte 5 controls the if select (table 8), the band select func tion bits bs1-bs0 (table 7) , the switching ports p3-p0 and the test modes (table 5). after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0 ' indicating byte 2 and a logi c '1' indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data by tes can be entered, where byte interpretation follows the same procedure, without re-addres sing the device. this procedure continues until a stop condition is received. the stop condition can be generated after an y data byte, if however it occurs during a byte transmission, the previous byte data is retained. to fa cilitate smooth fine tuning, th e frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. 2.2 read mode when the device is in read mode, the status byte read from the device takes the form shown table 3. bit 1 (por) is the power-on reset indicator, and this is set to a logic '1' if the vcc supply to the device has dropped below 3v (at 25 o c), e.g., when the device is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high th is indicates that the programmed information may have been corrupted and the device reset to power up condition. bit 2 (fl) indicates whether the device is phase locked, a logi c '1' is present if the device is locked and a logic '0' if the device is unlocked.
sl2610 data sheet 7 zarlink semiconductor inc. 2.3 programmable features synthesiser programmable divider function as described above. reference programmable divider function as described above. band selection the required mixer oscillator band and rf input is selected by bits bs1-bs0, within data byte 5, as defined in table 7. if selection the centre of the image reject pass band is selected by if as defined in table 8. charge pump current the charge pump current can be programmed by bits c1-c0 within data byte 4, as defined in table 6. ports p3-p0 these are configured as npn open collector buffers and programmed by bits p3- p0. logic ?1? = on. logic ?0? = off (high impedance); default on power up. in test modes, when te=1, ports p3-p0 respond according to t2-t0 respectively and previously transmitted data is lost. test mode the test modes are invoked by setting bits t2?t0 as described in table 5.
sl2610 data sheet 8 zarlink semiconductor inc. table 1 - reference division ratio r4 r3 r2 r1 r0 ratio 00 0 0 0 2 00 0 0 1 4 00 0 1 0 8 00 0 1 1 16 00 1 0 0 32 00 1 0 1 64 0 0 1 1 0 128 0 0 1 1 1 256 0 1 0 0 0 not allowed 01 0 0 1 5 01 0 1 0 10 01 0 1 1 20 01 1 0 0 40 01 1 0 1 80 0 1 1 1 0 160 0 1 1 1 1 320 1 0 0 0 0 not allowed 10 0 0 1 6 10 0 1 0 12 10 0 1 1 24 10 1 0 0 48 10 1 0 1 96 1 0 1 1 0 192 1 0 1 1 1 384 1 1 0 0 0 not allowed 11 0 0 1 7 11 0 1 0 14 11 0 1 1 28 11 1 0 0 56 11 1 0 1 112 1 1 1 1 0 224 1 1 1 1 1 448
sl2610 data sheet 9 zarlink semiconductor inc. table 2 - write data format (msb is transmitted first) table 3 - read data format (msb is transmitted first) a : acknowledge bit ma1,ma0 : variable address bits (see table 4) 2 14 -2 0 : programmable division ratio control bits r4-r0 : reference division ratio select (see table 1) c1,c0 : charge pump current select (see table 6) bs1-bs0 : band select bits (see table 7) if : if passband select (see table 8) te : test mode enable t2-t0 : test mode control bits when te=1 (see table 5) p3-p0 : p3-p0 port output states por : power on reset indicator fl : phase lock flag msb lsb address 11000ma1ma00a byte 1 programmable divider 02 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 c1c0r4r3r2r1r0a byte 4 control data if bs1 bs0 te p3/t2 p2/t1 p1/t0 p0 a byte 5 msb lsb address 11000ma1ma01a byte 1 status byte por fl 0 0 0 0 0 0 a byte 2
sl2610 data sheet 10 zarlink semiconductor inc. # programmed by connecting a 30 k ? resistor between pin and vcc table 4 - address selection table 5 - test modes * crystal and selected local oscillator need signals to enable charge pump test modes and to toggle status byte bit fl x -?don?t care? ma1 ma0 address input voltage level 0 0 0-0.1vcc 0 1 open circuit 1 0 0.4vvcc ? 0.6 vcc # 1 1 0.9 vcc - vcc te t2 t1 t0 test mode description 0 x x x normal operation 1 0 0 0 normal operation 1 0 0 1 charge pump sink * status byte fl set to logic ?0? 1 0 1 0 charge pump source * status byte fl set to logic ?0? 1 0 1 1 charge pump disabled * status byte fl set to logic ?1? 1 1 0 0 normal operation and port p0 = fpd/2 1 1 0 1 charge pump sink * status byte fl set to logic ?0? port p0 = fcomp 1 1 1 0 charge pump source * status byte fl set to logic ?0? port p0 = fcomp 1 1 1 1 charge pump disabled * status byte fl set to logic ?1? port p0 = fcomp
sl2610 data sheet 11 zarlink semiconductor inc. table 6 - charge pump current table 7 - band select c1 c0 current in a min. typ. max. 00+ 85 + 130 + 175 01+ 190 + 280 + 370 10+ 420 + 600 + 780 11+ 930 + 1300 + 1670 bs1 bs0 band selected 0 0 lo band 0 1 mid band 1 0 hi band 1 1 hi band if input centre of image reject passband passband bandwidth 0 57 mhz 6 mhz 0 44 mhz 6 mhz 1 36 mhz 8 mhz table 8 - if select function
sl2610 data sheet 12 zarlink semiconductor inc. figure 6 - crystal oscillator application figure 7 - ifamp output load condition for test purposes figure 8 - lo band vco application xtalcap xtal 47 pf 47 pf sl2610 to 50 ? load sl2610 ifop ifopb 5:1 c2 l1 r1 4k7 l2 1u5h 100pf d1 bb640 vt r2 1k 7pf r16 120nh 20r c1 lolowop lolowopb
sl2610 data sheet 13 zarlink semiconductor inc. figure 9 - mid band vco application figure 10 - hi band vco application r3 1k l3 36nh c10 7pf l4 82nh r4 4k7 c9 100pf d2 bb640 lomidop lomidopb vt c15 10r l5 22nh c16 100pf d3 bb555 5pf r19 l6 c14 c13 c12 c11 2p2 2p2 2p2 2p2 r17 10r r18 10r 4k7 r6 r5 1k vt 8.2nh lohiip lohiop lohiopb lohiipb
sl2610 data sheet 14 zarlink semiconductor inc. figure 11 - lo, mid and hi band input impedance figure 12 - low, mid and hi band noise figure versus frequency ch1 s 11 1 u fs start 50.000 000 mhz stop 900.000 000 mhz dev1 vcc=4.7v cor prm 12 mar 2002 15:10:11 1 2 3 4 1_: 152.31 -12.117 145.94 pf 90.000 000 mhz 2_: 150.74 -34.063 220 mhz 3_: 133.48 -62.813 500 mhz 4_: 111.79 -86.926 900 mhz
sl2610 data sheet 15 zarlink semiconductor inc. figure 13 - converter third order two tone intermodulation test condition spectrum, input referred, all bands figure 14 - second order two tone intermodulation test condition spectrum, input referred -14 dbm -56 dbm df (6 mhz) f1-df f1 f2 f2+df incident power from 50 ? source iim3; -42 dbc -14 dbm -54 dbm df f2-f1 f1 f2 incident power from 50 ? source iim2; -40 dbc x
sl2610 data sheet 16 zarlink semiconductor inc. figure 15 - converter output impedance (single ended) figure 16 - ifamp input impedance ch1 s 11 1 u fs start 32.000 000 mhz stop 60.000 000 mhz dev4 5.3v prm 26 nov 2002 13:38:57 1 2 3 3_: 101.43 -8.0313 347.67 pf 57.000 000 mhz 1_: 102.92 -5.043 36 mhz 2_: 102.48 -6.4883 44 mhz ch1 s 11 1 u fs start 30.000 000 mhz stop 60.000 000 mhz c? avg 16 prm 27 nov 2002 09:17:33 1 2 3 1_: 173.88 11.094 49.045 nh 36.000 000 mhz 2_: 178.89 10.016 44 mhz 3_: 185.77 04.922 57 mhz
sl2610 data sheet 17 zarlink semiconductor inc. figure 17 - ifamp output impedance (single ended) figure 18 - typical agc output l evel set versus agcbias voltage ch1 s 11 1 u fs start 30.000 000 mhz stop 60.000 000 mhz prm 27 nov 2002 08:59:45 1 2 3 1_: 58.967 8.8438 39.098 nh 36.000 000 mhz 2_: 59.295 11.096 44 mhz 3_: 60.443 14.813 57 mhz 100 105 110 115 120 0123456 agcbias voltage (v) output level (db v)
sl2610 data sheet 18 zarlink semiconductor inc. electrical characteristics test conditions (unless otherwise stated) t amb = -40 o c to 85 o c, vee= 0 v, vcc=vcca=vccd = 5 v + 5% these characteristics are guaranteed by either productio n test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. characteristic pin min. typ. max. units conditions supply current 163 196 ma all switching ports off. lo or mid band enabled input frequency range 50 500 mhz input impedance see figure 11 and refer to note 8. input noise figure 13 db tamb=27 o c, see figure 12, refer to note 2, no correction for external filtering. converter gain 10 8.5 14 12.5 db db at 36 mhz and 44 mhz if frequency. at 57 mhz if frequency. conversion gain from 50 ? single ended source to differential 200 ? load, refer to note 3. conversion gain to ifamp output 28 25 36 33 db db at 36 mhz and 44 mhz if frequency. at 57 mhz if frequency. conversion gain from 50 ? single ended source to 50 ? single-ended load with output transformer as in figure 7, see notes 2 and 3. gain variation within channel 0.4 1 db channel bandwidth 8 mhz within operating frequency range, see note (2), excluding interstage shaping filter ripple. converter input referred ip2 26 dbm see figure 14 and refer to notes 4 and 6. assuming ideal power match. converter input referred im2 -40 dbc see figure 14 and refer to notes 4 and 6. converter input referred ip3 7 dbm see figure 13 and refer to notes 4 and 6. assuming ideal power match. converter input referred im3 -42 dbc see figure 13 and refer to notes 4 and 6. input referred p1db 101 db v local oscillator operation range 50 550 mhz refer to note 7. local oscillator tuning range 68 200 225 465 mhz mhz with application as in figure 8. with application as in figure 9.
sl2610 data sheet 19 zarlink semiconductor inc. characteristic pin min. typ. max. units conditions lo phase noise, ssb @ 1 khz offset @ 10 khz offset @ 100 khz offset -55 -86 -109 dbc/hz dbc/hz dbc/hz with application as in figure 8 and figure 9 outside of pll loop bandwidth. lo temperature stability 80 khz/ o c application as in figure 8 and figure 9. no temperature compensation. lo turn on drift 100 khz application as in figure 8 and figure 9, frequency drift over 15 minute period from turn on at a fixed ambient temperature. no temperature compensation. lo to rf input leakage 60 db v application as in figures 8 and 9. lo vcc stability 0.5 mhz/v lo spurs due to rf pulling -52 dbc see note 5. hi band enabled input frequency range 200 870 mhz input impedance see figure 11 and refer to note 8. input noise figure 13.5 db tamb=27 o c, see figure 12, refer to note 2, no correction for external filtering. converter gain 10 8.5 14 12.5 db db at 36 mhz and 44 mhz if frequency. at 57 mhz if frequency. conversion gain from 50 ? single ended source to differential 200 ? load, refer to note 3. conversion gain to ifamp output 28 25 36 33 db db at 36 mhz and 44 mhz if frequency. at 57 mhz if frequency. conversion gain from 50 ? single ended source to 50 ? single-ended load with output transformer as in figure 7, see notes 2 and 3. gain variation within channel 0.4 1 db channel bandwidth 8 mhz within operating frequency range, see note 3, excluding interstage shaping filter ripple. converter input referred ip2 26 dbm see figure 14 and refer to notes 4 and 6. assuming ideal power match.
sl2610 data sheet 20 zarlink semiconductor inc. characteristic pin min. typ. max. units conditions converter input referred im2 -40 dbc see figure 14 and refer to notes 4 and 6. converter input referred ip3 7 dbm see figure 13 and refer to notes 4 and 6. assuming ideal power match. converter input referred im3 -42 dbc see figure 13 and refer to notes 4 and 6. input referred p1db 101 db v local oscillator operation range 200 1000 mhz refer to note 7. local oscillator tuning range 440 950 mhz with application as in figure 10. lo phase noise, ssb @ 1 khz offset @ 10 khz offset @ 100 khz offset -55 -86 -109 dbc/hz dbc/hz dbc/hz with application as in figure 10, outside of pll loop bandwidth. lo temperature stability 110 khz/ o c application as in figure 10. no temperature compensation. lo turn on drift 100 khz application as in figure 10, frequency drift over 15 minute period from turn on at a fixed ambient temperature. no temperature compensation. lo to rf input leakage 60 db v application as in figure 10. lo vcc stability 0.5 mhz/v lo spurs due to rf pulling -52 dbc see note 5. all bands converter output impedance 200 ? differential, see figure 15. image rejection 25 29 25 30 35 30 db db db at 36 mhz if frequency, if bit = 1. at 44 mhz if frequency, if bit = 0. at 57 mhz if frequency, if bit = 0. see table 8. ta m b = 0 o c to +85 o c. tank schematics and layouts as in recommended application. see figures 4 and 5. isolation between band inputs -60 dbc level of desired signal converted to if output through disabled band relative to signal converted through enabled band. composite output amplitude 3 dbm
sl2610 data sheet 21 zarlink semiconductor inc. characteristic pin min. typ. max. units conditions ifamp input frequency range 32 60 mhz input impedance 200 ? differential, see figure 16. gain 20 18.5 24 22.5 db db at 36 mhz and 44 mhz if frequency. at 57 mhz if frequency. voltage conversion gain from 200 ? differential source to differential load as contained in figure 7, see note 3. output impedance 100 ? differential, see figure 17. output limiting 3 2.7 vp-p vp-p at 36 mhz and 44 mhz if fequency. at 57 mhz if frequency. differential into load as in figure 7. ifamp opip3 135 db v two output tones at 2 mhz separation at 104 dbuv into load as in figure 7, see note 2. ifamp opim3 -62 dbc two output tones at 2 mhz separation at 104 dbuv into load as in figure 7, see note 2. agcbias leakage current 28 -100 -50 100 50 a a vee vagc1 vcc 1.5v vagc1 3.5v agcout voltage range 13 0.5 3 v max load current 20 a. agc output level set see figure 18. supply rejection -52 dbc spurs introduced on converted output relative to desired signal by a supply ripple voltage of 10 mv p-p in the range 1 khz to 100 khz (including external supply decoupling). synthesiser sda, scl input high voltage input low voltage input current leakage current hysterysis 19, 20 19, 20 3 0 -10 0.4 5.5 1.5 10 10 v v a a v input voltage =vee to vcc input voltage = vee to 5.5 v, vcc=vee sda output voltage 19 0.4 0.6 v v isink = 3 ma isink = 6 ma scl clock rate 20 400 khz
sl2610 data sheet 22 zarlink semiconductor inc. notes 1 all power levels are referred to 50 ?, and 0 dbm = 107 db v. 2 total system with final load as in figure 7, including an interstage if shaping filter with il of 2 db and characteristic impedance of 200 ? differential. 3 the specified gain is determ ined by the following formula; gs = gm + vtr where gs = gain as specified gm = gain as measured with specified load conditions vtr = voltage transformation ratio of transformer as in figure 7 4 two input tones within rf operating range at -14 dbm from 50 ? single ended source with 200 ? differential output load. dc output current must be shunted to vcc through suitable inductor, i.e. 10 h. 5 modulation spurs introduced on local oscillator thro ugh injection locking of th e local oscilla tor by an undesired rf carrier. desired carrier at 80 db v, undesired carrier at 90 db v at an offset frequency of f d plus 42+f c mhz, where f d is desired carrier frequency, f c is us chrominance sub carrier and 42 equals 7 channel spacings. 6 all intermodulation specifications are measured with a single-ended input. 7 operation range is defined as the region over which the oscillator presents a negative impedance. 8 target to achieve 6 db minimum s11. characteristic pin min. ty p. max. units conditions charge pump output current 16 see table 6. vpin16 = 2 v charge pump output leakage 16 + 3+ 10 na vpin16 = 2 v charge pump drive output current 15 0.5 ma vpin15 = 0.7 v crystal frequency 17, 18 4 16 mhz application as in figure 6. recommended crystal series resonance 10 200 ? 4 mhz parallel resonant crystal. external reference input frequency 17, 18 4 20 mhz sinewave coupled through 10 nf blocking capacitor. external reference drive level 18 0.2 0.5 vpp sinewave coupled through 10 nf blocking capacitor. phase detector comparison frequency .03125 0.25 mhz equivalent phase noise at phase detector -158 with 4 mhz crystal, ssb, within loop bandwidth. with fcomp = 125 khz rf division ratio 240 32767 reference division ratio see table 1. switching ports p0-p3 sink current leakage current 1, 5, 6, 14 10 10 ma a vport = 0.7 v vport = vcc address select input high current input low current 24 1 -0.5 ma ma see table 4. vin=vcc vin=vee
sl2610 data sheet 23 zarlink semiconductor inc. absolute maximum ratings all voltages are referred to vee at 0 v. characteristic min. max. units conditions supply voltage -0.3 6 v rf input voltage 117 db v transient condition only. all i/o port dc offsets -0.3 vcc+0.3 v total port current 20 ma storage temperature -55 150 o c junction temperature 125 o c power applied. package thermal resistance, chip to ambient 27 o c/w package paddle soldered to ground. power consumption at 5.25v 1 w esd protection 1 kv mil-std 883b method 3015 cat1
sl2610 data sheet 24 zarlink semiconductor inc. figure 19 - input and output interface circuits (rf section) v cc 50 ? 29 ifop 50 ? 30 ifopb agcout v cc 1nf 3, 7, 10 ip external to chip typical 133-j62 ? @ 500 mhz (see figure 10) low, mid, hi, rf input 13 20k agc out convopb 22 convop 100 ? 100 ? v cc 1.38 k 95 ? 25 26 ifip ifipb converter output if input if output lohiop 33 lohiopb 400 ? 400 ? 34 lohiip v bias lohipb 500 ? 32 lohi input & output lolowop lomidop v bias lolow and lomid outputs 37 39 lolowopb lomidopb 2.4 v 9k v cc 28 agcbias agcbias input 4, 8, 11 ipb v cc 38 40 23 35 40 k
sl2610 data sheet 25 zarlink semiconductor inc. figure 20 - input and output interface circuits (pll section) 200 a 13 xtalcap 18 17 xtal vccd 220 16 15 drive vccd pump 24 500 k vccd scl/sda ack * on sda only * vccd 120 k 40 k add p0, p1, p2, p3 reference oscillator sda/scl (pins 19 and 20) output ports (pins 1, 5, 6, 14) add input loop amplifier
c zarlink semiconductor 2004 all rights reserved. apprd. issue date acn package code previous package codes see note 8. 1 package outline for 40 lead qfn pull back lead (6 x 6 x 0.9 mm) 0.80
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